library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY altera;
use altera.altera_primitives_components.all;

entity hex_display is 
	port(	number			: in integer range 0 to 9;
			hex				: out std_logic_vector(6 downto 0));
end hex_display;

architecture hex_display_arch of hex_display is
	signal intermed		: std_logic_vector(6 downto 0);
begin
	WITH number SELECT
		hex 	<= 	"0000001" WHEN 0,
								"1001111" WHEN 1,
								"0010010" WHEN 2,
								"0000110" WHEN 3,
								"1001100" WHEN 4,
								"0100100" WHEN 5,
								"0100000" WHEN 6,
								"0001111" WHEN 7,
								"0000000" WHEN 8,
								"0000100" WHEN 9,
								"0110000" WHEN OTHERS;
end hex_display_arch;

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clk_divider is 
	port ( 	clk_in			: in std_logic;
				clk_en			: in std_logic := '1';
				clk_out 			: inout std_logic := '0' );
end clk_divider;

architecture clk_divider_arch of clk_divider is
begin
	process(clk_in)
		variable cur_count	: integer range 0 to 50000000;
	begin
		if rising_edge(clk_in) then
			if clk_en = '0' then
				cur_count := 0;
				clk_out <= '0';
			else
				if cur_count = 50000000 then
					clk_out <= '1';
				else
					cur_count := cur_count + 1;
				end if;
			end if;
		end if;
	end process;
end;